Arana platform automates the process of behavioral model creation, generation, optimization, and validation for analog, custom digital, memory and mixed-signal integrated circuits. It features Arana Top-Down Designer, Arana Bottom-Up Designer, Arana Model Optimizer, and Arana Model Validator. Arana Top-Down Designer supports behavioral model creation from specification or from templates, as well as automated calibration of model parameters against the transistor response and/or measurement data. Arana Bottom-Up Designer allows a circuit designer to automatically generate silicon-faithful parametric behavioral models—accounting for process, voltage, temperature, and loading variations—for functional verification. Both Arana Bottom-Up Designer and Top-Down Designer support hierarchical modeling and automated generation of formal analog assertions and model test benches. Arana Model Optimizer and Model Validator optimize and validate behavioral models against transistor level responses and characterization and/or measurement data.

Arana has been tested by leading semiconductor companies on over 40 pre-layout and post-layout production circuits including operational amplifiers, comparators, bias generators, switches, charge pumps, analog to digital converters, digital to analog converters, source drivers, phase locked loops, delay locked loops, dc-dc converters, low-voltage differential signaling (LVDS), and Serializer/Deserilizer (SerDes).

Arana generated models accelerate SPICE simulation by 100 to 1000 times for complex mixed-signal circuits. It enables mixed-signal full-chip design verification and functional sign off, architecture exploration, IP reuse, and test development.

Benefits Features Tools Benchmarks
  • Reduce silicon re-spins by enabling full-chip mixed-signal functional design verification
  • Reduce simulation turn-around time and simulation data
  • Quickly create highly efficient behavioral models without knowing language specifics
  • Ensure a formal way of defining circuit operational constraints for formal checking and allow custom silicon to be verified with digital-like verification methodology
  • Enable hierarchical characterization and electrical rule checking across PVT corners (by linking to Orora's Arche)
  • Enable hierarchical optimization, redesign and yield improvement of custom IC (by linking with Orora's Arsyn)
  • Facilitate silicon IP reuse and IP protection
  • Specification-driven model creation
  • Netlist-driven model generation
  • Pin-compatible with netlist
  • Automated hierarchical model validation
  • No testbench required to generate behavioral models
  • Automatically generate test benches for model validation
  • Technology-independent
  • Integrated with Cadence/Mentor/Synopsis
  • 100 to 1000 times faster than SPICE
  • Generate automatically formal analog assertions
  • User adjustable modeling accuracy
Arana Top-Down Designer
  • Create generic behavioral models from a circuit specification or from a template
  • Test benches will be automatically applied.
  • Pin assertion
  • Functional template selection
  • Easy template definition
  • Automated parameter calibration against transistor netlist and measurement

Arana Bottom-Up Designer
  • Netlist-driven model generation
  • Automatic circuit partitioning and recognition to re-group design hierarchy for model generation
  • Generate pin-compatible behavioral models
  • Derive analytic expressions for key circuit characteristics
  • Calculate small-signal linearized expressions
  • Calculate large-signal nonlinear expressions
  • Generate discrete z-domain functional models for switched-capacitor circuits
  • Generate Verilog-A/D/AMS models for custom digital integrated circuits
  • Generate models over process-voltage-temperature (PVT) corners

Arana Model Optimizer
  • Automatically optimize model parameters against transistor-level simulation or measurement data without using test benches for parameter extraction
  • Model calibration with layout parasitics
  • Model calibration over multiple PVT corners
  • Reuse circuit testbenches
  • User-defined model accuracy

Arana Model Validator
  • Automatically generate validation testbenches
  • Validate over specified PVT corners
  • Script-driven and fully reconfigurable to address specific validation needs
  • Built-in integrity, passivity and convergence checking
  • Generate validation report
  • Support hierarchical validation
  • Validation visualization
  • Can use multiple CPUs
Circuits Process # of transistors Transistor simulation time Model simulation time Speed up Accuracy
XAUI SerDes IBM 90nm 15,000 > 15 days 15 min (100K bits) 1200X 5%
4-CH 10-bit Source Driver 16V 2u CMOS 6,000 > 3 days 17 min 250X 0.1%
6-bit Current Steering DAC IBM 90nm 1,200 18 min 60 msec 300X 1%
DC-DC Converter TFT 180 39 min 2 min 20X 0.3%
8-bit ΔΣ ADC -- -- 1.6 hr 23 sec 256X 6%
Custom MCU 90nm 12,000 12.3 hr 90 sec 500X 10%
VCO IBM 90nm 56 251 sec 0.73 sec 340X 1%
High-Speed Comparator IBM 90nm 780 1.5 hr 82 sec 100X 3%