Arsyn platform automates the custom design and reuse of transistor integrated circuits. Arsyn takes a parametric netlist with various circuit topology, device type and size options as the input, and automatically finds a set of designs that meet the specifications for a given foundry process. Arsyn is tightly integrated with custom IC design environments and layout extraction programs, and addresses product yield and robustness as part of the design process.

With a breakthrough in automated equation generation and multiple-objective robust optimization, Arsyn has been demonstrated to use ten times less simulation runs and dramatically shorter turn-around time than competing products. With a proprietary architecture combining equation-based, simulator-based, and knowledge-based analog synthesis technologies, Arsyn has been proven most robust in finding best possible solutions for all types of custom IC designs.

Arsyn delivers enhanced productivity, design quality, product yield and robustness. Arsyn facilitates late-stage design specification changes, design reuse, and process migration. Arsyn pioneers template-driven custom-circuit synthesis. Based on an open architecture and industry standard database, Arsyn allows designers to capture design knowledge including circuit topologies, test benches, behavioral models and circuit constraints as a template, and to build optimized design platforms for their differential custom silicon intellectual properties. Examples include Arsyn-empowered custom PLL, ADC, and SerDes silicon compilers.

Arsyn has been applied to circuit optmization, circuit re-design, circuit process migration, and yield enhancement of various circuits including opamps, comparators, filters, switched capacitor circuits, I/O buffers, memory circuits, digital library cells, RF front ends, LCD driver circuits, phase-locked loops, SerDes, A/D and D/A converters. With its first shipment in 2000, Arsyn has aided designers in designing and optimizing custom IC products with over 1 billon-dollar shipments.

Benefits Features Tools
  • Improve design productivity
  • Optimize existing designs for improved performance
  • Ensure design meets the spec across PVT corners
  • Automatically resize a design and topology change for process migration
  • Qualification and optimization of a design under various process conditions
  • Examination of design trends under differing performance constraints
  • Embedding of design knowledge for reuse
  • Maximize product yield and robustness (Arsyn-RPD)
  • Technology independent (can handle bulk and SOI CMOS, BiCMOS, SiGe BiCMOS, precision bipolar, GaAs, PHEMY, HBT,...)
  • Topology independent
  • Multi-objective optimization
  • Robustness: able to find solutions independent of starting points.
  • Efficiency: Arsyn is built on an architecture that combines local and global optimization engines incorporating design mining based history learning
  • Optimization over multiple process corners and mismatching
  • Visualization that helps designers to make the tradeoff among multiple performance targets
  • Uses analytic equation generators and custom equation interpreter
  • Ability to drive a design to match a specified response in either the time or frequency domain.
  • Ability to choose from a set of potential good solutions, instead of one optimized solution
  • Use automatically generated design equations, constraints and behavioral models
  • Open architecture
  • Incremental synthesis
  • Multiple objective design tradeoff analysis using Circuit Performance Radar Chart (CPRC)
  • Perform simultaneous device sizing, topology, and process selection
  • Handle various design constraints including both inequality and curve matching
  • Adaptive solution space control and quick determination of infeasible design specification
Arsyn Parametric Characterization
  • Automatically characterize a design over process-voltage-temperature (PVT) corners
  • Easy setup of PVT corners
  • Parameter sensitivity to reveal principal parameters for optimization
  • Generate performance models for initial design exploration or optimization
  • Generate analytic expressions of circuit characteristics either by computer-algebraic analysis or by design of experiments (DOE)

Arsyn Equation and Constraint Generation
  • Automatic derivation of key circuit performance equations
  • Model order reduction to simply circuit parasitic equations and identify key parasitic parameters
  • Automated generation of design constraints

Arsyn Initial Design Exploration
  • Multiple parameters affect multiple performances
  • Real-time sweep analysis
  • Use rapid evaluation engine for design tradeoffs
  • Identify initial design points and architectures for fast convergence of design process
  • Enable architecture innovation

Arsyn Design Search and Optimization
  • Search the entire solution space for best candidates to meet the design specifications
  • Use a simulator or simplified expressions to evaluate a design candidate and accelerate the search process
  • Use a detailed simulator at late search stage for fine-grade optimization
  • Adaptive objective function
  • Combined local and global optimization

Arsyn Layout Verification and Parasitic-Aware Optimization
  • Automated inclusion of post-layout circuit parasitics by seamlessly integrating with third-party layout extraction programs
  • Side-by-side comparison of pre-layout and post-layout circuit performance and yield (RPD)
  • Pinpoint the layout parasitics that cause the design and yield problem
  • Parasitic screening
  • Automated inclusion of layout parasitics for re-optimization

Arsyn Design Migration
  • Multiple parameters affect multiple performances